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| TM HM-65162/883 2K x 8 Asynchronous CMOS Static RAM Description The HM-65162/883 is a CMOS 2048 x 8 Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which allows easy memory board layouts flexible to accommodate a variety of industry standard PROMs, RAMs, ROMs and EPROMs. The HM-65162/883 is ideally suited for use in microprocessor based systems with its 8-bit word length organization. The convenient output enable also simplifies the bus interface by allowing the data outputs to be controlled independent of the chip enable. Gated inputs lower operating current and also eliminate the need for pull-up or pull-down resistors. March 1997 Features * This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Fast Access Time . . . . . . . . . . . . . . . . . . . 70/90ns Max * Low Standby Current. . . . . . . . . . . . . . . . . . . . 50A Max * Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max * Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20A Max * TTL Compatible Inputs and Outputs * JEDEC Approved Pinout (2716, 6116 Type) * No Clocks or Strobes Required * Wide Temperature Range . . . . . . . . . . -55oC to +125oC * Equal Cycle and Access Time * Single 5V Supply * Gated Inputs - No Pull-Up or Pull-Down Resistors Required Ordering Information 70ns/20A HM1-65162B/883 HM4-65162B/883 90ns/40A HM1-65162/883 HM4-65162/883 90ns/300A HM1-65162C/883 TEMP. RANGE -55oC to 125oC -55oC to 125oC PACKAGE CERDIP CLCC F24.6 J32.A PKG. NO. Pinouts HM-65162/883 (CERDIP) TOP VIEW A7 HM-65162/883 (CLCC) TOP VIEW VCC NC NC NC NC NC PIN 29 A8 28 A9 27 NC 26 W 25 G 24 A10 23 E 22 DQ7 21 DQ6 DESCRIPTION No Connect Address Input Chip Enable/Power Down Ground Data In/Data Out Power (+5V) Write Enable Output Enable A7 A6 A5 A4 A3 A2 A1 A0 DQ0 1 2 3 4 5 6 7 8 9 24 VCC 23 A8 22 A9 21 W 20 G 19 A10 18 E 17 DQ7 16 DQ6 15 DQ5 14 DQ4 13 DQ3 A6 A5 A4 A3 A2 5 6 7 8 9 4 3 2 1 32 31 30 NC A0 - A10 E VSS/GND DQ0 - DQ7 VCC W G A1 10 A0 11 NC 12 DQ0 13 14 15 16 DQ1 DQ2 GND 17 NC 18 DQ3 19 DQ4 20 DQ5 DQ1 10 DQ2 11 GND 12 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 188 FN3001.1 HM-65162/883 Functional Diagram A1 A A2 A3 A4 A5 A6 A7 ROW ADDRESS BUFFER 7 ROW DECODER A 7 128 COLUMN DECODER AND DATA INPUT / OUTPUT (X8) 4 A G 4 A 1 OF 8 DQ0 THRU DQ7 128 128 X 128 MEMORY ARRAY 8 E COLUMN ADDRESS BUFFER W A0 A8 A9 A10 189 HM-65162/883 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . .1.5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance JA JC CERDIP Package . . . . . . . . . . . . . . . . 48oC/W 8oC/W CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W 12oC/W oC to +150oC Maximum Storage Temperature Range . . . . . . . . .-65 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26000 Gates CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Chip Enable High/Low Time . . . . . . . . . . . . . . . . . . . . . . . 40ns (Min) Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to VCC Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . 2.0V to 4.5V Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max TABLE 1. 65162/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTE 1) CONDITIONS VCC = 4.5V, IO = -1.0mA VCC = 4.5V, IO = 4.0mA VCC = 5.5V, G = 2.2V, or E = 2.2V, VI/O = GND or VCC VCC = 5.5V, VI = GND or VCC HM-65162B/883, IO = 0mA, VCC = 5.5V, E = VCC -0.3V HM-65162/883, IO = 0mA, VCC = 5.5V, E = VCC - 0.3V HM-65162C/883, IO = 0mA, VCC = 5.5V, E = VCC - 0.3V Standby Supply Current Operating Supply Current Enable Supply Current Data Retention Supply Current ICCSB ICCOP ICCEN ICCDR VCC = 5.5V, IO = 0mA, E = 2.2V VCC = 5.5V, G = 5.5V, (Note 2), f = 1MHz, E = 0.8V VCC = 5.5V, IO = 0mA, E = 0.8V HM-65162B/883, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V HM-65162/883, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V HM-65162C/883, IO = 0mA, VCC = 2.0V, E = VCC - 0.3V Functional Test NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. FT VCC = 4.5V (Note 3) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 2.4 -1.0 MAX 0.4 1.0 UNITS V V A PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Standby Supply Current SYMBOL VOH1 VOL IIOZ II ICCSB1 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 7, 8A, 8B -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -1.0 - 1.0 50 100 900 8 70 70 20 40 300 - A A A A mA mA mA A A A - 190 HM-65162/883 TABLE 2. HM-65162/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested. LIMITS GROUP A SUBGROUPS 9, 10, 11 HM-65162B /883 TEMPERATURE MIN 70 MAX HM-65162 /883 MIN 90 MAX HM-65162C /883 MIN 90 MAX UNITS ns PARAMETER Read/Write/ Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Selection to End of Write Address Setup Time Write Enable Pulse Write Write Enable Read Setup Time Data Setup Time Data Hold Time SYMBOL (1) TAVAX (NOTES 1, 2) CONDITIONS VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC (2) TAVQV 9, 10, 11 - 70 - 90 - 90 ns (3) TELQV 9, 10, 11 - 70 - 90 - 90 ns (5) TGLQV 9, 10, 11 - 50 - 65 - 65 ns (11) TELWH 9, 10, 11 45 - 55 - 55 - ns (12) TAVWL 9, 10, 11 10 - 10 - 10 - ns (13) TWLWH 9, 10, 11 40 - 55 - 55 - ns (14) TWHAX 9, 10, 11 10 - 10 - 10 - ns (17) TDVWH VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V 9, 10, 11 -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC 30 - 30 - 30 - ns (18) TWHDX 9, 10, 11 10 - 15 - 15 - ns Write Enable Pulse Setup Time Chip Enable Data Setup Time Address Valid to End of Write (20) TWLEH 9, 10, 11 40 - 55 - 55 - ns (21) TDVEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC TA +125oC 30 - 30 - 30 - ns (22) TAVWH VCC = 4.5V and 5.5V 9, 10, 11 -55oC TA +125oC 50 - 65 - 65 - ns NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. 191 HM-65162/883 TABLE 3. HM-65162/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC LIMITS HM65162B/883 PARAMETER Input Capacitance SYMBOL CIN CONDITIONS VCC = Open, F = 1MHz, All Measurements Referenced To Device Ground VCC = Open, F = 1MHz, All Measurements Referenced To Device Ground VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V, IO = -100A NOTES 1, 2 1, 3 TEMPERATURE +25oC +25oC MIN MAX 10 8 HM65162/883 MIN MAX 10 8 HM65162C/883 MIN MAX 10 8 UNITS pF pF I/O Capacitance CI/O 1, 2 1, 3 +25oC +25oC - 12 10 - 12 10 - 12 10 pF pF Chip Enable to Output ON Output Enable to Output ON Chip Enable High to Output In High Z Output Disable to Output in High Z Output Hold from Address Change Write Enable to Output in High Z Write Enable High to Output ON Output High Voltage NOTES: (4) TELQX (6) TGLQX (7) TEHQZ 1 1 1 -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC 5 5 - 35 0 5 - 50 5 5 - 50 ns ns ns (8) TGHQZ 1 - 35 - 40 - 40 ns (9) TAVQX 1 5 - 5 - 5 - ns (16) TWLQZ (19) TWHQX 1 1 0 40 - 0 50 - 0 50 - ns ns VOH2 1 VCC 0.4V - VCC 0.4V - VCC 0.4V - V 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 2. Applies to DIP device types only. 3. Applies to LCC device types only. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 7, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 192 HM-65162/883 Timing Waveforms (1) TAVAX (2) TAVQV ADDRESS (8) TGHQZ G (5) TGLQV E (6) TGLQX (3) TELQV Q (4) TELQX (9) TAVQX (7) TEHQZ NOTE: 1. W is High for a Read Cycle. FIGURE 1. READ CYCLE Addresses must remain stable for the duration of the read cycle. To read, G and E must be VIL and W VIH. The output buffers can be controlled independently by G while E is low. To execute consecutive read cycles, E may be tied low continuously until all desired locations are accessed. When E is low, addresses must be driven by stable logic levels and must not be in the high impedance state. (10) TAVAX ADDRESS (11) TELWH E (12) TAVWL W (16) TWLQZ Q (21) TDVEH D (13) TWLWH (20) TWLEH (19) TWHQX (14) TWHAX (17) TDVWH (22) TAVWH (18) TWHDX NOTE: 1. G is Low throughout Write Cycle. FIGURE 2. WRITE CYCLE I To write, addresses must be stable, E low and W falling low for a period no shorter than TWLWH. Data in is referenced with the rising edge of W, (TDVWH and TWHDX). While addresses are changing, W must be high. When W falls low, the I/O pins are still in the output state for a period of TWLQZ and input data of the opposite phase to the outputs must not be applied, (Bus contention). If E transitions low simultaneously with the W line transitioning low or after the W transition, the output will remain in a high impedance state. G is held continuously low. 193 HM-65162/883 Timing Waveforms (Continued) (10) TAVAX ADDRESS (22) TAVWH G (11) TELWH E (12) TAVWL W TGHQZ (15) Q (21) TDVEH D (17) TDVWH (18) TWHDX (13) TWLWH (14) TWHAX FIGURE 3. WRITE CYCLE II In this write cycle G has control of the output after a period, TGHQZ. G switching the output to a high impedance state allows data in to be applied without bus contention after TGHQZ. When W transitions high, the data in can change after TWHDX to complete the write cycle. Low Voltage Data Retention Intersil CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaran teed over temperature. The following rules ensure data retention: 1. Chip Enable (E) must be held high during data retention; within VCC -0.3V to VCC +0.3V. 2. On RAMs which have selects or output enables (e.g., S, G), one of the selects or output enables should be held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation. 3. Inputs which are to be held high (e.g., E) must be kept between VCC +0.3V and 70% of VCC during the power up and down transitions. 4. The RAM can begin operation > 55ns after VCC reaches the minimum operating voltage (4.5V). DATA RETENTION TIMING VCC VCC 02.0V 4.5V 4.5V >55ns E VCC -0.3V TO VCC +0.3V FIGURE 4. DATA RETENTION TIMING 194 HM-65162/883 Test Circuit DUT (NOTE 1) CL IOH + - 1.5V IOL EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance includes stray and jig capacitance. Burn-In Circuits HM-65162/883 CERDIP TOP VIEW F10 HM-65162/883 CLCC TOP VIEW VCC VCC C NC NC NC NC A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 NC A7 F10 F9 F8 F7 F6 F5 F4 F3 F2 F2 F2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC A7 VCC F11 F12 F1 F0 F13 F0 F4 F2 F2 F2 F2 F2 F2 F3 F9 F8 F7 F6 F5 A6 A5 A4 A3 A2 A1 5 6 7 8 9 10 4 3 2 1 C 32 31 30 29 28 A8 A9 F11 F12 A0 11 NC 12 DQ0 13 14 15 16 17 18 DQ1 DQ2 NC DQ3 GND 19 20 DQ4 DQ5 27 NC W 26 G 25 A10 24 E 23 DQ7 22 DQ6 21 F1 F0 F13 F0 F2 F2 F2 F2 F2 F2 NOTES: All resistors 47kW 5%. F0 = 100kHz 10%. F1 = F0 / 2, F2 = F1 / 2, F3 = F2 / 2 . . . F13 = F12 / 2. VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C = 0.01F Min. NOTES: All resistors 47kW 5%. F0 = 100kHz 10%. F1 = F0 / 2, F2 = F1 / 2, F3 = F2 / 2 . . . F13 = F12 / 2. VCC = 5.5V 0.5V. VIH = 4.5V 10%. VIL = -0.2V to +0.4V. C = 0.01F Min. 195 F2 HM-65162/883 Die Characteristics DIE DIMENSIONS: 180.3 x 194.9 x 19 1mils METALLIZATION: Type: Si - Al Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.7 x 105 A/cm 2 Metallization Mask Layout HM-65162/883 A3 A4 A5 A6 A7 VCC A8 A9 W G A2 A10 A1 A0 DQ0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6 E DQ7 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 196 |
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